The position was for MS/ Ph.D. with 2 years of experience, I was an MS graduate with 2 years exp. They needed someone who worked heavily on SerDes designing with various Analog/Mixed-signal circuits in the SerDes Tx and Rx block. As I was working on the same project, they were interested in my profile for the interview. The interview consisted of 8 rounds, started at 9 AM and ended at 4:30 PM. Qs are as follows: -Single and two stage op amp basic, gain, impedance calculation -Compensation technique(Miller, in any other as well) -Gain and Rout calculation for Differential pair, Diode connected based circuits -Cascode and cascade circuits -CML circuit (buffer and Latch), factors to consider while designing CML buffer and latches (W/L, I bias, R out, etc) -How tail current/impedence affect the output and circuit performance -Arch of SerDes Rx and Tx, about each module in it, draw the complete architecture -Parallel to serial converter, serial to parallel converter, circuit design -VGA and PA circuit of SerDes Rx -DFE (Rx), FFE (Tx) working -CDR module (both Analog and digital type) -Phase Frequency detector circuit design, why PFD over PD for CDR design -PLL and CDR differences and module level design -VCO design ( 30 GHz LC based in my project) -Inductor layout design, Q factor= (2X Pi X F X L)/R, metal used (Metal 6), center taped -architecture design, respective calculations, Sonnet tool -Simulink -Matlab coding for Mixed-signal analysis -Verilog-AMS in cadence -Negative setup and hold time -Why nand over nor -Setup and hold time -Op-amp as integrator, differentiator, respective equations -Widler bandgap reference circuit design -BJT based question and respective circuit analysis(KCL/KVL) -Linear voltage regulator (my project) complete analysis and design -Verilog basic and write a few modules code -How to remove/reduce noises in analog/mixed-signal design world (about decoupling -capacitors and linear voltage regulators), noise analysis. -Tools used to validate the CDR design and TX, RX blocks of theSerDes. It was a tough interview which is obvious for such a good position, well-experienced team. Some engineers who interviewed me were nice, while a few were very rude which is common(I had faced the similar type of rude engineers in past while being interviewed for other positions in Intel) but on the bright side, there are other engineers who do care and try to understand the candidates without directly judging them.