its good all SV UVM Questions Project questions so prepare well for the interview like tlm ports SV testbench events Semaphore I2C Clock synchronisation NVme Flow WHY PCIE all other questions

OT- aptitude, digital, network theory Interview- 3 technical 1 hr Digital, sta, verilog, Finite state machine, test bench, mux related questions, 3 rounds of technical interview, 1 hr round, last round with director, asked about project, all digital verilog and fifo questions, 10110 seq detector, puzzles were there,