They started asking me about analog IC design questions like different topologies such as common gate, common source, common drain configurations, I answered then they asked me about folded cascode. I said my career focus is physical design(Backend digital ASIC). Then they said ok and asked me about the PD concepts. They asked about ASIC design flow, CTS, the tools used for PD, Floor planning, power planning, placement, TCL scripting. Then they asked about difference between a Latch and a flipflop. They asked about physical verification(DRC,LVS, ERC and PEX) and the tools used for it and the challenges faced. I answered almost all and then said you have all the necessary background. The interview went for around 30 to 40 mins.