Me postulé en persona. Acudí a una entrevista en SmartDV Technologies (Chennai) en sep 2024
Entrevista
Good interview with the good panel members .it was an average question everything related to the system Verilog UVM perl verific language and their syntax how to use those variables
Me postulé en línea. El proceso tomó 3 días. Acudí a una entrevista en SmartDV Technologies (Bengaluru) en sep 2025
Entrevista
The interview process typically has three stages:
Written / Online Test – Covers digital electronics, Verilog/SystemVerilog basics, C programming, and some aptitude/number system problems.
Technical Interviews (1–2 rounds) – Focus on digital design fundamentals (flip-flops, FSMs, counters), Verilog/SystemVerilog coding tasks, and UVM methodology basics (driver, monitor, scoreboard, coverage). Candidates may also be asked about their academic projects.
HR / Managerial Round – General discussion about background, interest in verification, work culture fit, and salary/relocation details.
Preguntas de entrevista [1]
Pregunta 1
How I Answered:
I explained that blocking assignments (=) execute sequentially, one after the other, like normal C statements, and they can cause race conditions if used in clocked always blocks.
Non-blocking assignments (<=) allow all right-hand side values to be evaluated first and then update the left-hand side at the end of the time step, making them ideal for modeling synchronous logic like flip-flops.
Acudí a una entrevista en SmartDV Technologies (Bangalore Rural)
Entrevista
It happened one full day. I underwent three rounds.Two virtual technical and one direct technical .only basics questions in digital electronics,vlsi,oops were asked in all the three rounds . May be they will conduct one general hr round
Preguntas de entrevista [1]
Pregunta 1
asked to draw half adder .number conversions were asked