5 rounds of interviews 1 with hiring manager, 1 presentation, 2 technical, 1 interview with director There is also a take-home assignment Questions were okay. Asked how an RTL code is synthesized i.e equivalent gate level netlist, cdc and metastability, reset synchronizer, filter sfgs, filter transfer function and optimization on critical path by adding delay on the sum of integrator instead of the output, sta, scan, uvm basics, simple 2ff sync, derate and ocv, power estimation, etc