It was a remote interview with length about 1 hour. I had the interview with preficient engineer, not manager. I did not get offer, but it was a good experience.
Preguntas de entrevista [1]
Pregunta 1
Design sequence detector with logic circuit diagram
Me postulé a través de un reclutador. El proceso tomó más de 2 meses. Acudí a una entrevista en Qualcomm (Raleigh, NC) en ago 2014
Entrevista
Started with a Recruiter contacting me via LinkedIn. An exchange of resume lead to a phone interview with the hiring manager and a technical team member. The phone conversation went well, conversation flowed, questions were discussed both technical and leadership, and what is sometimes a 15 minute planned conversation went on pleasantly for an hour. An invitation for an on-site interview was extended. Travel planning went smoothly, all via email. My hotel was just down the road from the offices, so I had no problem arriving early to the interview. The start time had been delayed multiple times, so each meeting was very short, clipping discussions and making design-on-the-fly tasks very difficult. Lunch with the hiring manager and another team member, was very nice, pleasant and relaxed, even though more technical questions came up in the conversation. I submitted my trip expenses, and was informed in a confirmation email, that it could take up to 90 days for reimbursement. I'm still waiting, and it's been 80 days.
Preguntas de entrevista [2]
Pregunta 1
Given a white-board diagram of a block with a FIFO, and verbal description of the block's inputs & outputs, write on the withe board the Verilog or SystemVerilog for the design. I had 15 minutes. Why would you want someone who goes straight to code, with no planning? That usually results in spaghetti code that has to be rewritten.
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.