After writing the test at university career fair, received a mail from HR for a phone interview. Had 2 technical rounds of 45 min each. The first round was taken by the hiring manager who asked basic questions on Verilog coding, caches, pipelines, data forwarding, branch prediction and FIFO design. The second interview was tougher with questions on instruction cache hit latency, multi-threading, branch misprediction, livelock, setup time, hold time, clock skew/jitter, Dennard scaling and its issues and different transistor level implementations of a mux. The whole process took 3 months and I had to constantly contact the HR for an update on my status.

Met on a zoom meeting for first round, second round were three separate meetings with engineers, third is with manager. Each round was deeply technical, ranging from rtl design to fsm design to theoretical architecture design.