Me postulé en línea. Acudí a una entrevista en NVIDIA
Entrevista
HR contacted me and set up the interview. 60 minutes interview each. The first interview was easier, the second interview was comparatiely harder. Questions covered topics from Computer Architecture, FIFO depth, RTL design, encoders , basic C codes and Systemverilog.
Preguntas de entrevista [1]
Pregunta 1
Computer Architecture, FIFO depth calculation, how to design Power, Performance, or Area-efficient RTLs, also some questions regarding pipeline hazards.
hr reach out, first interview with 1 h, then 3 interviews back to back, then last round with manager. Very quick response and feedback, good interviewers and good quetions and so on
Me postulé a través de una recomendación de un empleado. Acudí a una entrevista en NVIDIA (Santa Clara, CA) en ago 2025
Entrevista
First Screening Round
* 2 basic RTL Questions, 1 Scripting
* Blocking vs non blocking, reg vs wire
* Python scripting question: file I/O, basic string parsing
* 2nd RTL question: Basic 2 stage adder, design Verilog module given circuit description
* Some resume questions
Second Screening Round
* Advanced scripting question on retiming registers
* RTL question on accumulating data per address
* Some theoretical FIFO questions (no code)
* Packed vs unpacked arrays in depth
Panel Round
First Round
* Basic scripting question on data conversion and string parsing (CSV)
* Open-ended question on finding an error in a mux-based programmable delay circuit
* Resume questions
Second Round
* Designing a 10:1 mux using 3 4:1 muxes
* 80:20 to 8:2 module, FIFO depth
Third Round (Hiring Manager)
* Fibonacci Sequence in Python: Iterative and Recursive
* Fibonacci Sequence in Verilog: Serial approach, FSM Design
* Detailed discussion about team functions, responsibilities, day-to-day job
Fourth Round
* 4x4 multiplier in Verilog
* Optimize to pipeline multiplies
* Optimize to use a single MAC unit and serially feed in data
* Second largest sum in a Python list
Fifth Round
* Debugging a Perl script
* A lot of questions about intermediate expressions in Verilog and data-loss
Preguntas de entrevista [1]
Pregunta 1
First Screening Round
* 2 basic RTL Questions, 1 Scripting
* Blocking vs non blocking, reg vs wire
* Python scripting question: file I/O, basic string parsing
* 2nd RTL question: Basic 2 stage adder, design Verilog module given circuit description
* Some resume questions
Second Screening Round
* Advanced scripting question on retiming registers
* RTL question on accumulating data per address
* Some theoretical FIFO questions (no code)
* Packed vs unpacked arrays in depth
Panel Round
First Round
* Basic scripting question on data conversion and string parsing (CSV)
* Open-ended question on finding an error in a mux-based programmable delay circuit
* Resume questions
Second Round
* Designing a 10:1 mux using 3 4:1 muxes
* 80:20 to 8:2 module, FIFO depth
Third Round (Hiring Manager)
* Fibonacci Sequence in Python: Iterative and Recursive
* Fibonacci Sequence in Verilog: Serial approach, FSM Design
* Detailed discussion about team functions, responsibilities, day-to-day job
Fourth Round
* 4x4 multiplier in Verilog
* Optimize to pipeline multiplies
* Optimize to use a single MAC unit and serially feed in data
* Second largest sum in a Python list
Fifth Round
* Debugging a Perl script
* A lot of questions about intermediate expressions in Verilog and data-loss