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      Búsquedas relacionadas: Evaluaciones de Microchip Technology | Empleos en Microchip Technology | Sueldos en Microchip Technology | Prestaciones en Microchip Technology
      Entrevistas en Microchip TechnologyEntrevistas para el cargo de Staff Design Engineer en Microchip TechnologyEntrevista en Microchip Technology


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      Entrevista para Staff Design Engineer

      15 jun 2020
      Candidato de entrevista anónimo
      San Jose, CA
      Sin ofertas
      Experiencia negativa
      Entrevista difícil

      Solicitud

      Me postulé en línea. El proceso tomó 3 semanas. Acudí a una entrevista en Microchip Technology (San Jose, CA) en ago 2019

      Entrevista

      This position for the former Actel FPGA division. Their San Jose, CA facility is a ghost town (I saw very few people inside the building.). Since they have about 5% of the total FPGA business (They do a niche flash based FPGA mainly suited for aerospace / military use, but being too slow for the mainstream part of the FPGA business.), I am not too surprised that they do not have too many people working there. The manager responded to the job application the next day. It appears that s/he was very skeptical of someone else other than the candidate being interviewed (perhaps, s/he got burned in the past), so s/he insisted me to do a WebEx session. While this is for an FPGA position s/he did ask various entry level analog and signal processing questions (I did not do well on those areas since I do not care much about them.). The computer architecture / FPGA questions were not bad for me (experienced candidate), but they are not really easy for someone without much experience other than taking college level ASIC / FPGA type classes (this includes MSEE level NCG people). I did reasonably well, so I was invited for an on-site interview. The on-site had 5 people for about 4 hours. The first person was a specialist in high speed SERDES (Serializer / Deserializer). While I had actual design experience using SERDES, this person went into asking questions about how the internals of the SERDES worked. I did say that I do not have the design experience of designing the internals of SERDES, but this person completely ignored me, and forced me to answer questions I did not really know. It appears that this person wanted to show off the skills s/he has. Second person was not really important. Made me do short digital design questions similar to what college juniors will do in an exam. Third person was the manager, and continued doing the same basic fundamental knowledge questions done during the WebEx screening. Fourth question was rather old person similar to manager's age. S/he asked various basic questions, but also went over my resume in more details than the manager. S/he was rather dismissive of my prior design experience. The last person was perhaps the nicest person, and did not ask any questions. Just wanted to have a chat somewhat related to the job. The manager ghosted me, and never heard back from (I did not follow up, either). One last thing is that this firm is fairly insistent on submitting unofficial transcript of the college work during the interview process. Since I do not like sharing my unofficial transcript with anyone, I did not provide it. There was another manager who asked for the same 3 weeks prior to the WebEx screening, so be aware. Overall, I did not have a good experience, and I recommend avoiding this firm if you care about your career.

      Preguntas de entrevista [1]

      Pregunta 1

      (manager basic fundamental knowledge questions) - What is the FPGA design flow? - What strategies do you use to get timing closure? - Write RTL code (Verilog or VHDL) that reserves bit order of a vector (i.e., 8 bit ).
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