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      Búsquedas relacionadas: Evaluaciones de Marvell Technology | Empleos en Marvell Technology | Sueldos en Marvell Technology | Prestaciones en Marvell Technology
      Entrevistas en Marvell TechnologyEntrevistas para el cargo de Design Verification Engineer en Marvell TechnologyEntrevista en Marvell Technology


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      Entrevista para Design Verification Engineer

      24 jul 2021
      Empleado anónimo
      Oferta aceptada
      Experiencia positiva
      Entrevista promedio

      Solicitud

      El proceso tomó 2 semanas. Acudí a una entrevista en Marvell Technology en jul 2021

      Entrevista

      Interview had 3 technical rounds. Round 1 - Managerial followed by technical (50 minutes) Round 2 - Technical (1hr 15 min) Round 3 - Technical (1 hr) Round 1 and 2 were based on digital electronics and Verilog. Round 3 along with digital electronics, Verilog also had questions on OOPS, Interrupts , DSA, C++. Major focus was on basic concepts of everything mentioned above.

      Preguntas de entrevista [1]

      Pregunta 1

      1. Basics of digital electronics like combinational gates, mux, flip flops, registers, finite state machines, Verliog/ RTL code. 2. Difference between i) setup and hold time, ii) synchronous and asynchronous rests(explain through verilog coding) , iii) mealy and moore iv) tasks and function v) combinational and sequential vi) blocking and non-blocking statements vii) inter and intra statement delay 3. Verilog code for flip flops and finite state machines. 4. Maximum operating frequency of the circuit which had a combo logic between 2 flip flops. (HINT: Setup and hold time equation's based ques) 5. Varying what factor in the equation of setup and hold time can the violation of setup and hold time can be eliminated. (HINT: By varying combo propagation time.) 6. Flip flop conversions, truth tables, a logic implementation through mux, kmaps. 7. ASIC flow diagram, what is netlist, what is RTL. 8. OOPS concepts, sorting algorithms, time complexity. 9. Types of interrupts, what happens when interrupt is called. 10. What is function, what is class. How a class is called. 11. Detecting a sequence through mealy and moore state machines.
      Responder pregunta
      13

      Otras evaluaciones sobre las entrevistas para el cargo de Design Verification Engineer en Marvell Technology

      Entrevista para Design Verification Engineer

      17 mar 2026
      Candidato de entrevista anónimo
      San Jose, CA
      Sin ofertas
      Experiencia negativa
      Entrevista promedio

      Solicitud

      Acudí a una entrevista en Marvell Technology (San Jose, CA)

      Entrevista

      Phone interview with an engineer. No questions about my experience or information about the job. He was only interested in the test bench structure at another company. The interview was not very long and felt very awkward.

      Preguntas de entrevista [1]

      Pregunta 1

      The interviewer was interested in a specific test bench structure I worked with at another company.
      Responder pregunta
      1

      Entrevista para Design Verification Engineer

      25 nov 2025
      Candidato de entrevista anónimo
      Petah Tikva
      Sin ofertas
      Experiencia positiva
      Entrevista fácil

      Solicitud

      Acudí a una entrevista en Marvell Technology (Petah Tikva)

      Entrevista

      2 hours interview in the beginning they introduce them selves then the company and the team then ask you to introduce your self and your projects then 2 technical questions.

      Preguntas de entrevista [1]

      Pregunta 1

      : first given a block which you can see its interface and what would you check in order to make sure that the component works as it should the component was something like a memory. second question is a simple leet code question.
      Responder pregunta

      Entrevista para Design Verification Engineer

      3 may 2024
      Candidato de entrevista anónimo
      Bengaluru
      Sin ofertas
      Experiencia negativa
      Entrevista fácil

      Solicitud

      Me postulé en línea. El proceso tomó 4 semanas. Acudí a una entrevista en Marvell Technology (Bengaluru) en abr 2024

      Entrevista

      This role is for low power verif senior engineer, easy interview screening with project manager asked mostly on resume and previous projects , they don’t even get back to you with an automated email also such a waste of candidate time , don’t ever consider Marvell unlesss you think they gonna really hire someone

      Preguntas de entrevista [1]

      Pregunta 1

      Explain pg gate sims, few upf concepts
      Responder pregunta