Round 1: Written Test --> 7 subjective questions were asked. Particular Topics: 1) 2 on Verilog(HDL for JK FF with set and reset) and one was based on instantiation of module) 2) 1 on STA 3) 1 on FSM( detect 11001 and 11011 simultaneously with overlap) 4) 1 on CMOS function Implementation with sizing of transistors(using Euler Path) 5) Frequency divider( divide by 3, with 50% duty cycle) 6) HDL was given, and they asked to make a hardware implementation of it Round 2: Interview --> It went about 55 minutes.

It was a 30-minute interview that was primarily focused on technical skills. I was also asked to give a 10-minute presentation on a verification-related project. The interview was engaging and enjoyable. The interviewer's had over 20 years of industry experience and demonstrated deep technical knowledge. The discussion was insightful, and I appreciated the opportunity to interact with someone with such extensive expertise. Overall, it was a positive experience with a strong focus on technical understanding and practical verification concepts.