Me postulé a través de un reclutador. Acudí a una entrevista en Apple (Cupertino, CA) en abr 2021
Entrevista
2 screening rounds + 6 final rounds on the same day.
Questions from system verilog coding, synthesis, RTL lint check, cdc check, logic design, low power design etc.
Few interviews were centered around the resume.
Preguntas de entrevista [5]
Pregunta 1
Async fifo design and SDC contraints for it.
Pulse synchronizer cross clock domains.
Me postulé en línea. Acudí a una entrevista en Apple en feb 2026
Entrevista
1 - Applied to a different team but wasn't a good fit (was referred to another team). 2 - Got scheduled an interview with the hiring manager. A successful interview would lead to 6 more interviews with engineers. 3 - Didn't make it past the technical screen for my level.
Preguntas de entrevista [1]
Pregunta 1
FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
The interview process for VLSI digital design typically includes an initial screening, technical interviews covering digital design concepts, RTL coding, timing analysis, logic synthesis, verification, problem-solving, and sometimes a practical coding task.
Me postulé en línea. Acudí a una entrevista en Apple
Entrevista
applied online, got call after a long time, 1 round video call interview, talking about hardware design flow, low power. Asked a question someone already posted here long time ago, surprised.