<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description:&nbsp;</h2><p>This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.</p><p></p><p>The IOTS Pathfinding team is seeking a motivated and detail-oriented Engineer Intern to join our team in Guadalajara. In this role, you will support readiness and scalability for next-generation high-speed I/O technologies (PCI Express, UPI, CXL, USB) by assisting in technology pathfinding projects critical to future server platforms and Intel&#39;s data center leadership.<span> </span></p><p></p><p>You will also develop automated simulation workflows to evaluate full PCIe channel and circuit topologies using simulation tools, extracting realistic channel models, running equalization sweeps, and analyzing results to identify performance bottlenecks and optimization opportunities for next-generation PCIe links.</p><p></p><p>You will collaborate with engineers across Intel&#39;s I/O community and, as needed, interact with external industry organizations. Under mentorship, you will help execute parametric studies and optimization sweeps to explore SI/PI performance and manufacturability tradeoffs, assist with correlating simulations to lab/bench measurements, and contribute to documentation such as a best-practices / design-guidelines report and reusable modeling workflows for design teams.</p><p></p><p><b>Key Responsibilities </b></p><ul><li><span>Develop and maintain an automated end-to-end workflow to simulate PCIe channel/circuit topologies using simulation tools, including repeatable run scripts and standardized inputs/outputs. </span></li><li><span>Extract realistic channel models (e.g., S-parameters / behavioral representations as applicable) from full topology descriptions and ensure model quality/consistency for simulation use. </span></li><li><span>Set up and run transmitter/receiver equalization sweeps (TX FIR/FFE, CTLE/DFE, adaptation presets, etc. as supported) and capture sensitivity to channel conditions and topology variations. </span></li><li><span>Analyze simulation outputs to identify channel performance bottlenecks (e.g., loss, reflections, crosstalk, discontinuities) and propose mitigation actions and topology/parameter improvements. </span></li><li><span>Automate post-processing, data reduction, and reporting (plots, tables, margin/compliance metrics) to enable fast comparison across topologies and equalization settings. </span></li><li><span>Deliver a reusable simulation testbench (configs, scripts, templates) and a technical report quantifying improvements and documenting recommended settings, assumptions, limitations, and best practices for next-gen PCIe compliance work. </span></li><li><span>Present progress and findings in team meetings; collaborate with SI/PI, board/package design, and validation engineers to review results, align on assumptions, and iterate on topology and equalization recommendations. </span></li></ul><p></p><p><b>Behavioral Traits </b></p><ul><li><span>Eagerness to learn and apply new technical concepts. </span></li><li><span>Sense of ownership and accountability for assigned tasks. </span></li><li><span>Work effectively in a team-oriented environment. </span></li><li><span>Proactive, organized, and able to manage multiple tasks. </span></li><li><span>Open to feedback and continuous improvement. </span></li></ul><p></p><p><b>What You Will Learn </b></p><ul><li><span>Hands-on experience building and running PCIe channel simulations for full circuit/topology use cases (package &#43; board &#43; connectors/cables as applicable). </span></li><li><span>Practical exposure to channel model extraction and handling (e.g., S-parameters and related representations) and how model quality impacts link performance predictions. </span></li><li><span>Skills in workflow automation for batch runs, parametric sweeps, and post-processing (e.g., scripting, data reduction, plotting) </span></li><li><span>Understanding of transmitter/receiver equalization concepts and sweeps (e.g., TX FIR/FFE, CTLE/DFE) and how EQ settings interact with loss/reflections/crosstalk to determine margin. </span></li><li><span>Experience documenting results in a reusable simulation testbench and a summary report (assumptions, limitations, comparisons, and recommendations) oriented towards next-gen PCIe compliance readiness.</span></li></ul><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.</p><p>Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.</p><p></p><p><b>Minimum Qualifications:</b></p><ul><li><span>Pursuing a Bachelor, Master&#39;s degree or PhD&#39;s Degreen in Electronics</span><span> or Electrical Engineering, Computer Engineering, Mechatronics, or a related technical field (with at least 1 year remaining before graduation). </span></li><li><span><span> </span>3&#43; months of experience in Electrical Engineering (both Digital and Analog Electronics). </span></li><li><span>Advance English level. </span></li><li><span>Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship). </span></li></ul><p></p><p><b>Preferred Qualifications:</b></p><ul><li><span>Knowledge of high-speed serial link / PCIe channel fundamentals (insertion/return loss, impedance discontinuities, crosstalk, reflections, mode conversion) and how they impact eye/margin. </span></li><li><span>Experience (academic or project) with channel/circuit simulation for high-speed links using ICAT and/or Seasim (or similar SI simulation environments). </span></li><li><span>Familiarity with TX/RX equalization (TX FIR/FFE, CTLE/DFE) and ability to set up sweeps, interpret results, and identify bottlenecks/trade-offs. </span></li><li><span>Comfort working with S-parameters and frequency-domain metrics; familiarity with VNA/TDR concepts, de-embedding, and basic correlation of simulation vs. measurement is a plus. </span></li><li><span>Understanding PCIe channel building blocks (packages, PCBs, vias, connectors, transmission lines, stack-ups/materials) and practical considerations that drive loss and discontinuities. </span></li><li><span>Programming/scripting skills for automation and data analysis (Python preferred; MATLAB also acceptable), including handling large parametric sweep datasets and generating summary plots/tables. </span></li><li><span>Technical communication skills-able to document assumptions, results, and recommendations clearly and present findings to SI/PI, design, and validation stakeholders.</span></li></ul><p></p><p> </p><p></p><p></p>A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.<p style="text-align:inherit">&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp;</p><h2>Job Type:</h2>Student / Intern<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (Mexico)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location:&nbsp;</h2>Mexico, Guadalajara<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p></p><p><b>Work Model for this Role</b></p>This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.