Pregunta de entrevista de NVIDIA

PHONE : 1. Pass by value/ pass by reference. Write a function to swap 2 variables - ll u use pass by value or reference ? 2. Do the same to swap 2 objects (how does it change) 2. Detect 11010 sequence with moore and mealy state machines. 3. Use of const ? What ll happen if you declare above 2 objects as const. 4. Explain NB assignment and blocking assignment. About event regions. 5. Fibonacci -- iterative solution and recursive solution. 6. Disadvantages of a recursive solution. 7. Output of this code fragment : reg a,b,c,d,w; assign w = a; initial begin a = 2; c=5; b<=c; a=5; end what is output of all registers. 8. Explain RISC pipeline. What is the problems. 9. Explain about uvm driver etc. ONSITE : round 1: Round Robin Arbiter Design round 2 : (1) Given a stack class implementation (LIFO) - there are 3 methods - push(), pop(), isempty(). Write a class using objects of given class to implement a FIFO. (2) Make best performance Implement the dist functionality in c++. Given a set of weights mimic to provide randomization skewed to the specification (Basically, write a function that would do something similar to a 'dist' in system verilog). round 3 : Given a divide by 3 state machine. Implement a divide by 5 statemachine. How many vectors are needed to verify it. So the circuit takes serial bit inputs and asserts if the number is a multiple of 3 or 5. round 4 : Circuits project. Basic pipeline architecture. Design a pipeline for a histogram processor. In every cycle we get an instruction (CLR, ADD INCR). Handle dependencies using bypass. round 5 : Given a producer and consumer. They are clocked with the same clock. Producer produces 80 writes for 100 clocks (no random). Consumer reads 8 times per 10 clocks. Find the FIFO depth. Write RTL and verify.

Respuestas de entrevistas

Anónimo

17 oct 2016

It need not add up to 1. In system verilog, typical use of dist does not constrain this. It can be 60:60:60 -- which means probability of 1,2, 3 is 1/3rd.

Anónimo

17 oct 2016

thanks for your answers, they are extremely helpful. good luck to your job hunting

Anónimo

17 oct 2016

The histogram processor is something custom. It could be correlated to the DLX pipeline because of memory bottlenecks and dependencies.

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Anónimo

14 oct 2016

Hi! Thanks for you detailed interview questions, for the round3 onsite, what exactly do you mean by divide by 3 statemachine, is it clock frequency divided by 3? or sth else

Anónimo

15 oct 2016

For the dist functionality, If we assume there are 3 numbers, (1,2,3) to be randomly picked from the pool. are we assuming that the total weight (say 60%,30%,10%) needs to be added up to 100%?. If so, we can simply use a index= rand()%10, then assign index=0 to randomnumber=1, index=1,2,3 to randomnumber=2, index=4,5,6,7,8,9 to randomnumber=3.

Anónimo

15 oct 2016

Is the histogram processor similar to MIPS or RISC processor, I think histogram is very specific to GPU application?

Anónimo

17 oct 2016

Hi, first thanks for sharing this with us! For the FIFO question, is there any difference between randomization and without randomization. I think the answer at least for the 20 data randomization case is 32, since the worst case of write is 160 consecutive write, on the reading side, it takes 160/10 =16 , 16*8=128 data, the difference is 32, which is the FIFO size

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Anónimo

14 oct 2016

Hi. It is not a clock divider. Assume you are getting 1 bit input for every cycle. This state machine is supposed to assert high if it sees that the sequence received is a multiple of 3. Something like a sequence detector. But final moore output is if sequence was multiple of 3. Ex : if 0,1,1 are inputs for every cycle. output for every cycle is 1,0,1 (because 0 and 3 are multiples of 3).

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