Basic UVM and Verilog questions. This was a Screening round. uvm component vs uvm object, 16:1 mux using 4:1, axi protocol, purpose of new() in uvm, etc, 4 input nand gate using 2 input
Preguntas de entrevista [1]
Pregunta 1
mealy vs moore, which is better in terms of rtl coding
Me postulé en línea. Acudí a una entrevista en Qualcomm (Bengaluru) en dic 2025
Entrevista
round 1 was basic digital electronics.. i answered max all of them.. round 2 not went well..asked about coa.. and also i don"t know anything about c programming.. so they asked about it..
Acudí a una entrevista en Qualcomm (Santa Clara, CA)
Entrevista
The Qualcomm interview was a well-structured and technically intensive process. It began with a screening round that focused on digital design fundamentals and SystemVerilog concepts. Subsequent rounds included detailed questions on UVM methodology, debugging techniques, and real-world verification challenges. I was asked to explain past project experiences, testbench architecture, and corner case handling. The interviewers were friendly, professional, and encouraged clear, logical thinking. They seemed interested in both technical skills and problem-solving approach. There was also a focus on communication and collaboration, which made the interview more engaging. Overall, it was a challenging yet rewarding experience that encouraged deep technical discussion.