Me postulé en línea. El proceso tomó 1 día. Acudí a una entrevista en AMD (Austin, TX) en feb 2012
Entrevista
After applying online, received phone call a few days later from a lower-level employee with a couple of years experience. The phone interview was completely technical in nature, with no personality or leadership questions. Got invited to be flown down for an on-site interview, but was already in town, so was able to interview the next day.
On-site interview was four 45-minute interviews with employees of different divisions within the working group, each one-on-one, and all of them completely technical with no non-technical questions. They also provided lunch with entry-level employees from working group.
Was given the impression that would receive a follow-up contact within a few days but did not receive any contact until I inquired over a month later.
Overall, the people were friendly and the campus was nice. Got the feeling that people enjoyed working there.
Preguntas de entrevista [1]
Pregunta 1
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Preguntas de entrevista [1]
Pregunta 1
Tell me the difference between combinational and sequential logic
I was not well prepared, It was basic q and a related to my current role and some basic OSI questions, Also interviewer was great he gave me time to understand the question and helped me with the hints
Preguntas de entrevista [1]
Pregunta 1
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling,
Arth overflow
Stack over
1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?.
2. Also, How to write those test cases. ?